During manufacture of computer hardware components, for example hard disk drives, it is necessary to “debug” the components to ensure that they are working properly before packaging and shipping for sale. These components may comprise a large number of functional elements or blocks, e.g., microprocessors, buffer memory, and internal test points. Often these functional elements are combined in a single chip or circuit, for example, an application-specific integrated circuit (ASIC). Known testing methods involve using parallel debug ports with a large number of output pins to access data from each of these possible data points during testing. However, on a test chip it is less desirable to have a large number of pins due to the large surface area required to mount a pin. The more silicon used, the greater the cost of the chip. Thus, from a practical standpoint, only a limited number of internal signals can be monitored at one time. Also, parallel ports have bandwidth limitations, which further limit the amount of information that can be output. Further, there is no method to communicate with the chip since these are output only ports. Also, as the speed of microprocessors rises, the high data output (clock) rate across a parallel bus increases and can cause electrical noise and skew issues.
The information included in this Background section of the specification, including any references cited herein and any description or discussion thereof, is included for technical reference purposes only and is not to be regarded subject matter by which the scope of the invention is to be bound.